1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device including a circuit detecting a defect of a memory cell.
2. Description of the Background Art
In the process of manufacturing a memory cell, a short-circuit possibly occurs between a gate of a memory cell transistor and a bit line, between the gate of the memory cell transistor and a storage node of a memory cell capacitor, or between adjacent storage nodes, because of etching residue or foreign matters.
Such a short-circuit causes malfunction of the memory cell. Therefore, a conventional semiconductor memory device includes a test circuit for testing a memory cell array, to detect any defect.
As regards the short-circuit between the storage nodes, the speed of detecting the short-circuit can be increased by increasing potential difference between the short-circuited storage nodes.
The bit line connected to the sense amplifier, however, has the amplitude up to 0V only. Therefore, in the conventional semiconductor integrated circuit, a potential of 0V is applied as the data of xe2x80x9cLxe2x80x9d level to the storage node of one cell, and a potential higher than normal is applied as the xe2x80x9cHxe2x80x9d level data, to the storage node of the other cell of the pair.
When the high potential corresponding to the xe2x80x9cHxe2x80x9d data is increased so as to widen the potential difference, the potential difference between the storage node and the cell plate also becomes larger, possibly damaging a dielectric film existing between the storage node and the cell plate.
On the other hand, as the potential on the xe2x80x9cHxe2x80x9d data cannot be increased, it takes time for detection.
An object of the present invention is to provide a semiconductor memory device including a circuit capable of efficiently detecting a short-circuit between storage nodes.
In accordance with the present invention, the semiconductor memory device includes: a memory cell array including memory cells each having a memory cell capacitor storing charges and a memory cell transistor, word lines connected to the gates of memory cell transistors and bit lines connected to storage nodes of the memory cell capacitors; and a sense amplifier connected to the bit lines and sensing the charges stored in the memory cells as data. The sense amplifier circuit amplifies the bit line to a ground potential or a positive power supply potential in a normal operation mode, and amplifies the bit line to a positive power supply potential or a negative power supply potential in a test mode. Preferably, the semiconductor memory device further includes an activation signal generating circuit generating an activation signal controlling activation of the sense amplifier circuit in the normal operation mode and generating a test activating signal controlling activation of the sense amplifier circuit in the test mode. The sense amplifier circuit includes a circuit setting the bit line to the ground potential when the activation signal is activated, and setting the bit line to the negative potential when the test activating signal is activated.
Specifically, a substrate potential of the memory cell transistor is used as the negative potential. Alternatively, the negative potential is supplied externally.
Specifically, in the test mode, storage nodes adjacent to each other are set to the positive power supply potential and the negative potential, respectively.
Specifically, the semiconductor memory device further includes a supplying circuit supplying from the outside a cell plate voltage to be supplied to the cell plate of the memory cell capacitor, and by the supplying circuit, the cell plate voltage is set to an intermediate potential between the positive power supply potential and the negative potential.
Therefore, in the semiconductor memory device described above, the potential difference between the storage nodes can be made higher than in the conventional semiconductor memory device. Accordingly, it is possible to enhance the ability to, detect any short-circuit between the storage nodes.
Further, as a higher stress can be applied as compared with the conventional semiconductor memory device, the test time can be reduced.
Further, it is possible not only to detect a defective cell by the detection test in the wafer test stage but to replace a defective cell with a redundant cell. This leads to improved production yield.
As the potential difference is widened by utilizing a negative potential, stress applied to unrelated portions other than the storage node can be prevented.
Further, as the internally generated substrate potential itself is used as the negative potential, increase in the number of circuits to implement the present function can be suppressed.
Alternatively, by supplying the negative potential from the outside, the chip operation in the test mode can be stabilized.
Further, by adjusting the cell plate voltage, the burden on the dielectric film between the storage node and the cell plate can be alleviated. In a test in which a high stress is applied, a margin for the chip can be increased.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.